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ds04-22005-1e fujitsu semiconductor data sheet assp communication control ieee1394-scsi tailgate mb86616 n n n n description the mb86616 is the lsi for protocol conversion to connect scsi devices to the ieee 1394 bus. this lsi integrates a 1394 controller compliant with the ieee standard for high performance serial bus (ieee std. 1394-1995, or firewire standard) and an scsi protocol controller compliant with the scsi-fast20 standard on a single chip. it also incorporates the f 2 mc-16f as a processor for controlling the individual on-chip controllers, providing ease of control. the ieee 1394 controller unit has two ports for use in a cable environment and contains a differential transceiver and a comparator. it supports s400 data transfer rates. in addition, it supports the chain command to continuously issue request packets for data transmission and reception, improving the efficiency of data transfer. the scsi protocol controller unit conforms to 8-bit fast20 scsi, enabling data transfer at a maximum of 20 mbyte/s. for the scsi bus terminal, the unit contains a totem pole type of single-end driver/receiver so that it can drive the scsi bus directly. while inheriting the at architecture of the f 2 mc-16/16h family, the instruction set for the f 2 mc-16f cpu core incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. n n n n pac k ag e 144-pin plastic lqfp (fpt-144p-m08)
mb86616 2 n n n n features ? ieee 1394 controller unit ? compliant with the ieee standard for high performance serial bus (ieee std. 1394-1995 ? physical and link layer modules integrated on a single chip ?two cable ports ? data transfer rates supported : s100, s200, s400 ? data buffer dedicated to asynchronous transmission/reception ? 2-kbyte (1/2/4 bank-switchable) , transmission/reception shared data buffer ? 128-byte buffer dedicated to asynchronous transmission and 128-byte buffer dedicated to asynchronous re- ception ? automatic separation of the packet header and data upon reception and automatic packetization of information upon transmission ? 32-bit crc generation and check functions ? chain transfer function for data transfer sequence ? 4- and 4-conductor cables supported ? scsi protocol controller unit ? dedicated to initiator operation ? fast-20 data transfer (8-bit) synchronous transfer : 20 mbps max. (maximum offset value of 15) asynchronous transfer : 5 mbps max. ? internal 16-byte fifo data register ? totem pole type of fast20 single-end driver/receiver ? 28-bit transfer byte counter enabling simultaneous transfer of up to 256 mbytes of data ? f 2 mc-16f unit ? minimum instruction execution time : 40.7 ns (at 24.576 mhz) ? instruction set optimized for controller applications ? instruction set supporting high-level languages (including c) and multi tasking ? miscellaneous ? supply voltage : 3.3 v and 5 v power supplies ? package : lqfp-144 (fpt-144p-m08)
mb86616 3 n n n n pin assignment drawing (top view) (fpt-144p-m08) v dd3 v ss md0 md1 md2 sv ss rst bsy sel sv ss sv dd5 v ss v dd3 msg cd io sv ss atn req ack sv ss dbp db7 db6 sv ss sv dd5 v ss v dd3 db5 db4 db3 sv ss db2 db1 db0 sv ss 108 105 100 95 90 85 80 75 73 1 5 10 15 20 25 30 35 36 a05 a04 a03 a02 a01 test1 v ss v dd3 d15 d14 d13 d12 d11 d10 d09 d08 d07 v ss v dd3 d06 d05 d04 d03 d02 d01 d00 v dd3 v ss n.c. pwr3 pwr2 pwr1 linkon pmode v ss v dd3 v dd3 v ss a06 a07 a08 a09 a10 a11 v ss v dd3 a12 a13 a14 a15 a16 a17 a18 v dd3 v ss test2 wr rd test3 p74 p75 p76 p90/int0 p91/int1 v dd3 v ss p92 p93 cs test4 test5 test6 72 70 65 60 55 50 45 40 37 av ss av dd tpbias0 tpa0 tpa0 tpb0 tpb0 av dd av ss av ss av dd tpbias1 tpa1 tpa1 tpb1 tpb1 av dd av ss cps r0 av dd av ss rf fil av dd av ss sclk v ss n.c. testp modec modeb modea reset v ss v dd3 109 110 115 120 125 130 135 140 144 mb86616
mb86616 4 n n n n pin assignment table pin no. i/o pin name pin no. i/o pin name pin no. i/o pin name pin no. i/o pin name 1 ? v dd3 37 ? v dd3 73 ? v dd3 109 ? v dd3 2 ? v ss 38 ? v ss 74 ? v ss 110 ? v ss 3 id md0 39 id reset 75 id pmode 111 id/o a06 4 id md1 40 id modea 76 o linkon 112 id/o a07 5 id md2 41 id modeb 77 id pwr1 113 id/o a08 6 ? sv ss 42 id modec 78 id pwr2 114 id/o a09 7 si/o rst 43 o testp 79 id pwr3 115 id/o a10 8 si/o bsy 44 ? n.c. 80 ? n.c. 116 id/o a11 9 si/o sel 45 ? v ss 81 ? v ss 117 ? v ss 10 ? sv ss 46 id sclk 82 ? v dd3 118 ? v dd3 11 ? sv dd5 47 ? av ss 83 id/o d00 119 id/o a12 12 ? v ss 48 ? av dd 84 id/o d01 120 id/o a13 13 ? v dd3 49 ao fil 85 id/o d02 121 id/o a14 14 si/o msg 50 ao rf 86 id/o d03 122 id/o a15 15 si/o cd 51 ? av ss 87 id/o d04 123 id/o a16 16 si/o io 52 ? av dd 88 id/o d05 124 id/o a17 17 ? sv ss 53 ao r0 89 id/o d06 125 id/o a18 18 si/o atn 54 i cps 90 ? v dd3 126 ? v dd3 19 si/o req 55 ? av ss 91 ? v ss 127 ? v ss 20 si/o ack 56 ? av dd 92 id/o d07 128 o test2 21 ? sv ss 57 ai/o tpb1 93 id/o d08 129 iu/o wr 22 si/o dbp 58 ai/o tpb1 94 id/o d09 130 iu/o rd 23 si/o db7 59 ai/o tpa1 95 id/o d10 131 o test3 24 si/o db6 60 ai/o tpa1 96 id/o d11 132 id/o p74 25 ? sv ss 61 ao tpbias1 97 id/o d12 133 id/o p75 26 ? sv dd5 62 ? av dd 98 id/o d13 134 id/o p76 27 ? v ss 63 ? av ss 99 id/o d14 135 id/o p90/int0 28 ? v dd3 64 ? av ss 100 id/o d15 136 id/o p91/int1 29 si/o db5 65 ? av dd 101 ? v dd3 137 ? v dd3 30 si/o db4 66 ai/o tpb0 102 ? v ss 138 ? v ss 31 si/o db3 67 ai/o tpb0 103 o test1 139 id/o p92 32 ? sv ss 68 ai/o tpa0 104 id/o a01 140 id/o p93 33 si/o db2 69 ai/o tpa0 105 id/o a02 141 iu/o cs 34 si/o db1 70 ao tpbias0 106 id/o a03 142 o test4 35 si/o db0 71 ? av dd 107 id/o a04 143 o test5 36 ? sv ss 72 ? av ss 108 id/o a05 144 o test6
mb86616 5 i/o types: id : digital input pin (with pull-down resistor) o : digital output pin id/o : digital input/output pin (with pull-down resistor) iu/o : digital input/output pin (with pull-up resistor) si/o : scsi input/output pin ai : analog input pin ao : analog output pin ai/o : analog input/output pin
mb86616 6 n n n n pin description 1. ieee 1394 interface 2. scsi interface 3. internal cpu pins (for normal operation mode) note that the pin functions covered in this section are enabled only in the normal operation mode (with the modea pin = l) . signal name i/o function tpa0, tpa1 i/o tpa positive-signal input/output pin at ieee 1394 port tpa0 , tpa1 i/o tpa negative-signal input/output pin at ieee 1394 port tpb0, tpb1 i/o tpb positive-signal input/output pin at ieee 1394 port tpb0 , tpb1 i/o tpb negative-signal input/output pin at ieee 1394 port tpbias0, tpbias1 o common-voltage reference voltage output pin at ieee 1394 port signal name i/o function req , ack , atn , msg , cd , io , rst , bsy , sel i/o scsi control signal input/output pins db0 to db7 i/o input/output pins for scsi data bus dbp i/o parity bit input/output pins for scsi data bus signal name i/o function a01 to a18 o address output pins d00 to d15 i/o data input pins wr o write strobe signal output pin rd o read strobe signal output pin cs o pin to output the external flash rom chip enable signal. this signal is output for accessing an address from f80000h to ffffffh in memory space. p74 to p76 p90 to p93 i/o general-purpose input/output port pins md0 to md2 i cpu block mode setting pins. connect all of these pins to gnd on this device.
mb86616 7 4. cpu interface (for external cpu mode) note that the pin functions covered in this section are enabled only in the external cpu mode (with the modea pin = h) . 5. other pins (continued) signal name i/o function a01 to a09 i external cpu address input pin d00 to d15 i/o external cpu data input/output pin cs i pin to input the chip select signal to this device wr i pin to input the write strobe signal to this device rd i pin to input the read strobe signal to this device int0 o interrupt request output pin for the ieee 1394 block int1 o interrupt request output pin for the scsi block signal name i/o function reset i reset signal input pin. leave this pin at the l level while the ieee 1394 block is operating with cable supplied power. modea i pin for setting the operation mode of this device. l input : use the internal cpu. h input : use an external cpu to control this device without using the internal cpu. modeb, modec i connect these pins to gnd. sclk i reference clock input pin for the internal pll (24.576 mhz) rf o connect this pin to gnd via a 5.1 k w resistor. fil o external filter circuit connection pin for the internal pll r0 o connect this pin to gnd via a 5.1 k w resistor. cps i pin to input power supplied through the ieee 1394 cable. the pin detects cable supplied power of 0 to 33 v (an external resistor is re- quired to regulate/divide the voltage) . connect this pin to gnd if the device is not powered through the ieee 1394 cable. pmode i power input evaluation pin. l input : operate the device with power supplied through the ieee 1394 cable. (only the ieee 1394 block operates with the cable supplied power, with the other blocks left in the reset state.) h input : operate the device with the system power supply. pwr1 to pwr3 i pins to set the power_class bit in the self-id packet which is transmitted during operation with power supplied through the ieee 1394 cable. note : the power_class in the self-id packet transmitted during opera- tion with the system power supply depends not on these pins but on the settings of the pwr bits (bits 2 to 0) in physical register #4.
mb86616 8 (continued) 6. power/gnd pins signal name i/o function linkon o output pin for detection of link-on packet reception. this pin outputs the h level signal upon reception of the link-on packet during operation with power supplies through the ieee 1394 cable. the out- put signal level changes to l the moment the pmode signal becomes h. the output from this pin remains unchanged with pmode = h. leave this pin open when not in use. testp, test1 to test6 o test pin. leave it open. n.c. ? leave this pin open. signal name i/o function v dd3 ? 3.3 v digital power supply pin v ss ? digital ground pin sv dd5 ? 5 v power supply pin for scsi i/o sv ss ? ground pin for scsi i/o av dd ? 3.3 v analog power supply pin av ss ? analog ground pin
mb86616 9 n n n n block diagram ? normal operation mode pll cpu bus sclk fil rf f 2 mc-16f cpu clock frequency divider f 2 mc-16f bus external interface ram 4 kbyte external interrupt 16 bit timer 3 ieee1394 block dreqa dwra drda dreqb dwrb drdb exchange block dma data bus scsi block tpa0/tpa1 tpb0/tpb1 tpa0/tpa1 tpb0/tpb1 tpbias0/tpbias1 rst bsy sel msg cd io req ack atn dbp db0 to db7 cs wr rd d00 to d15 a01 to a18
mb86616 10 ? external cpu mode cpu-i/f int0, int1 cs wr rd d00 to d15 a01 to a09 sclk fil rf pll cpu bus tpa0/tpa1 tpa0/tpa1 tpb0/tpb1 tpb0/tpb1 tpbias0/tpbias1 ieee1394 block exchange block dma data bus clock frequency divider scsi block dreqa dwra drda dreqb dwrb drdb rst bsy sel msg cd io req ack atn dbp db0 to db7
mb86616 11 n n n n functions of blocks ? cpu block this block controls the individual blocks. it incorporates the f 2 mc-16f as the core and ram, 16-bit timers (3 channels) , and an external interrupt controller as peripheral circuits. ? ieee 1394 block this block controls the ieee 1394 interface. ? scsi block this block controls the scsi interface. ? pll circuit this block generates clock signals for individual blocks from the reference clock signal generated by the clock module. reference oscillation frequency : 24.576 mhz clock frequency for cpu block : 24.576 mhz clock frequency for ieee 1394 block : 393.216 mhz (for bus) , 49.152 mhz (for internal operation) clock frequency for scsi block : 39.322 mhz clock frequency for exchange block : 39.322 mhz
mb86616 12 n n n n internal registers 1. memory space ffffffh (external flash rom) exchange block scsi block ieee 1394 block cpu block external rom/external bus mode general registers inaccessible area f80000h 002300h 002200h 002100h 002000h 001100h 000100h 0000c0h 000000h ram
mb86616 13 2. cpu block internal registers (continued) address (hex) write operation read operation resource name register name abbrevi- ation register name abbrevi- ation 000000 to 000006 system reserved area ? system reserved area ?? 000007 port-7 data register pdr7 port-7 data register pdr7 port 7 000008 system reserved area ? system reserved area ?? 000009 port-9 data register pdr9 port-9 data register pdr9 port 9 00000a to 00000f (reserved) ? (reserved) ?? 000010 to 000016 system reserved area ? system reserved area ?? 000017 port-7 direction register ddr7 port-7 direction register ddr7 port 7 000018 system reserved area ? system reserved area ?? 000019 port-9 direction register ddr9 port-9 direction register ddr9 port 9 000019 to 00002f (reserved) ? (reserved) ?? 000030 interrupt/dtp enable register enir interrupt/dtp enable register enir dtp/external interrupt 000031 interrupt/dtp source register enrr interrupt/dtp source register enrr 000032 request level set register elvr request level set register elvr 000033 to 00003f (reserved) ? (reserved) ?? 000040 timer control status #0 tmcsr0 timer control status #0 tmcsr0 16-bit timer #0 000041 000042 (reserved) ? 16 bit timer #0 tmt0 000043 000044 16-bit timer reload #0 tmrlr0 (reserved) ? 000045 000046 to 000047 (reserved) ? (reserved) ?? 000048 timer control status #1 tmcsr1 timer control status #1 tmcsr1 16-bit timer #1 000049 00004a (reserved) ? 16 bit timer #1 tmt1 00004b 00004c 16 bit timer reload #1 tmrlr1 (reserved) ? 00004d 00004e to 00004f (reserved) ? (reserved) ??
mb86616 14 (continued) address (hex) write operation read operation resource name register name abbrevi- ation register name abbrevi- ation 000050 timer control status #2 tmcsr2 timer control status #2 tmcsr2 16-bit timer #2 000051 000052 (reserved) ? 16 bit timer #2 tmt2 000053 000054 16 bit timer reload #2 tmrlr2 (reserved) ? 000055 000056 to 00008f (reserved) ? (reserved) ?? 000090 to 00009e system reserved area ? system reserved area ?? 00009f delayed interrupt source generate/reset register dirr delayed interrupt source generate/reset register dirr delayed interrupt 0000a0 standby control register stbyc standby control register stbyc low power consumption 0000a1 to 0000a2 (reserved) ? (reserved) ?? 0000a3 middle address control register macr (reserved) ? external pin 0000a4 high address control register hacr (reserved) ? external pin 0000a5 external pin control register epcr (reserved) ? external pin 0000a6 to 0000a7 (reserved) ? (reserved) ?? 0000a8 watchdog timer control register twc watchdog timer control register twc watchdog timer 0000a9 time-base timer control register tbtc time-base timer control register tbtc time-base timer 0000aa to 0000af (reserved) ? (reserved) ?? 0000b0 interrupt control register 0 icr0 interrupt control register 0 icr0 interrupt controller 0000b1 interrupt control register 1 icr1 interrupt control register 1 icr1 0000b2 system reserved area ? system reserved area ? 0000b3 system reserved area ? system reserved area ? 0000b4 interrupt control register 4 icr4 interrupt control register 4 icr4 0000b5 interrupt control register 5 icr5 interrupt control register 5 icr5 0000b6 system reserved area ? system reserved area ?
mb86616 15 (continued) address (hex) write operation read operation resource name register name abbrevi- ation register name abbrevi- ation 0000b7 interrupt control register 7 icr7 interrupt control register 7 icr7 interrupt controller 0000b8 interrupt control register 8 icr8 interrupt control register 8 icr8 0000b9 interrupt control register 9 icr9 interrupt control register 9 icr9 0000ba interrupt control register 10 icr10 interrupt control register 10 icr10 0000bb system reserved area ? system reserved area ? 0000bc system reserved area ? system reserved area ? 0000bd system reserved area ? system reserved area ? 0000be system reserved area ? system reserved area ? 0000bf interrupt control register 15 icr15 interrupt control register 15 icr15
mb86616 16 3. ieee 1394 block internal registers (continued) address (hex) write operation read operation register name abbrevia- tion register name abbrevia- tion 002000 mode-control mctl mode-control mctl 002002 (reserved) ? flag & status flst 002004 instruction-fetch inst instruction-fetch inst 002006 interrupt-mask set register intm interrupt-code display register intc 002008 (reserved) ? reception acknowledge display register rack 00200a a-buffer data port transmit register sadp a-buffer data port receive register radp 00200c d-buffer data port transmit register sddp d-buffer data port receive register rddp 00200e (reserved) ? (reserved) ? 002010 (reserved) ? (reserved) ? 002012 transmission async-des-id set register sadid (reserved) ? 002014 transmission async-pkt-param set register sapp reception async-pkt-param display register rapp 002016 transmission async-data-length set register sadl reception async-data-length display register radl 002018 transmission async-ex-tcode set register saet reception async-ex-tcode display register raet 00201a transmission async-source-bus- id set register sasid reception async-source-id display register rasid 00201c transmission async-rcode set register sarc reception async-rcode display register rarc 00201e transmission async-des-offset set register (upper) sadou reception async-des-offset display register (upper) radou 002020 transmission async-des-offset set register (middle) sadom reception async-des-offset display register (middle) radom 002022 transmission async-des-offset set register (lower) sadol reception async-des-offset display register (lower) radol 002024 total chain data-length set register (upper) csdlu remaining chain data byte counter (upper) crbcu 002026 total chain data length set register (lower) csdll remaining chain data byte counter (lower) crbcl 002028 chain transmission des-id set register cdid ping time monitor ptmn 00202a chain transmission des-offset set register (upper) cdou (reserved) ? 00202c chain transmission des-offset set register (middle) cdom (reserved) ?
mb86616 17 (continued) address (hex) write operation read operation register name abbrevia- tion register name abbrevia- tion 00202e chain transmission des-offset set register (lower) cdol (reserved) ? 002030 chain transmission data-length set register csdl received packet transfer rate display register pspd 002032 chain retry-limit set register crlm cycle-timer-monitor display register (upper) ctmu 002034 (reserved) ? cycle-timer-monitor display register (lower) ctml 002036 (reserved) ? revision display register revm 002038 phy/link register address set register plra phy/link register address set register plra 00203a phy/link register access port (write) wplap phy/link register access port (read) rplap 00203c to 0000fe (reserved) ? (reserved) ?
mb86616 18 4. scsi block internal registers 5. exchange block internal registers address (hex) write operation read operation register name abbrevia- tion register name abbrevia- tion 002100 bus device id bdid bus device id bdid 002102 scsi control sctl scsi control sctl 002104 scsi command scmd scsi command scmd 002106 transfer mode tmod transfer mode tmod 002108 interrupt sense ints interrupt sense ints 00210a scsi diagnostic control sdgc phase sense psns 00210c (reserved) ? scsi block status ssts 00210e (reserved) ? scsi error status serr 002110 phase control pctl phase control pctl 002112 extend transfer counter tce extend transfer counter tce 002114 data register (scsi output) dreg data register (scsi input) dreg 002116 temporary (scsi output) temp temporary (scsi input) temp 002118 transfer counter (high) tch transfer counter (high) tch 00211a transfer counter (mid) tcm transfer counter (mid) tcm 00211c transfer counter (low) tcl transfer counter (low) tcl 00211e req/ack timeout set rato modified byte counter mbc 002120 to 0000fe (reserved) ? (reserved) ? address (hex) write operation read operation register name abbrevia- tion register name abbrevia- tion 002200 mode control emod mode control emod 002202 signal control esctl signal sense essns 002204 data port (input) edpi data port (output) edpo 002206 to 0000fe (reserved) ? (reserved) ?
mb86616 19 n n n n absolute maximum ratings (vss = 0 v) *1 : for scsi i/o *2 : maximum supply current which can flow in steady state. exceeding it is allowed only within 1 second per lsi unit excluding the scsi i/o. *3 : within 50 ns warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit min. max. power supply voltage v dd3 v ss - 0.5 4.0 v v dd5 *1 v ss - 0.5 6.0 v input voltage v i3 v ss - 0.5 v dd3 + 0.5 v v i5 *1 v ss - 0.5 v dd5 + 0.5 v output voltage v o3 v ss - 0.5 v dd3 + 0.5 v v o5 *1 v ss - 0.5 v dd5 + 0.5 v ambient storage temperature tst - 55 + 125 c operating junction temperature tj - 40 + 125 c output current *2 i o i ol = 4 ma 14 ma overshoot ? v dd3 + 1.0 *3 v undershoot ? v ss - 1.0 *3 v
mb86616 20 n n n n recommended operating conditions (vss = 0 v) *1 : d00 to d15 *2 : md0 to md2, reset , modea to modec, pmode, pwr1 to pwr3, a01 to a18, cs , wr , rd , p74 to p76, p90 to p93, test2 to test6. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol values unit min. typ. max. power supply voltage 3.3 v power supply v dd3 3.0 3.3 3.6 v 5 v power supply (for scsi-i/o) v dd5 4.5 5.0 5.5 v h level input voltage cmos normal *1 v ihn v dd3 0.65 ? v dd3 + 0.3 v cmos schmitt *2 v ihs v dd3 0.80 ? v dd3 + 0.3 v scsi v ihsc 2.0 ? v dd5 + 0.3 v l level input voltage cmos normal *1 v iln v ss ? v dd3 0.25 v cmos schmitt *2 v ils v ss ? v dd3 0.20 v scsi v ilsc v ss ? 0.8 v differential input voltage (for data transfer) ieee1394 v idd 118 ? 260 mv differential input voltage (for arbitration) ieee1394 v ida 168 ? 265 mv common-mode input voltage ieee1394 s100 v cm 100 1.165 ? 2.515 v s200 v cm 200 0.935 ? 2.515 v s400 v cm 400 0.523 ? 2.515 v receiving input jitter ieee1394 ?? ? 0.315 ns receiving input skew ieee1394 ?? ? 0.8 ns operating temperature ta 0 ? 70 c
mb86616 21 n n n n electrical characteristics 1. dc characteristics the dc characteristics guarantee the worst-case values of static characteristics of the input/output buffers within the recommended operating condition ranges. (1) digital i/o pins (v dd3 = 3.3 0.3 v, vss = 0 v, ta = 0 to 70 c) *1 : maximum current that flows when the output pin is connected to vdd or vss, for one second per lsi pin. *2 : the input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor is used. (2) scsi i/o pins (v dd5 = 5.0 0.5 v, vss = 0 v, ta = 0 to 70 c) parameter symbol conditions values unit min. typ. max. h level output voltage v oh i oh = - 4 ma v dd - 0.5 ? v dd v l level output voltage v ol i ol = 4 ma v ss ? 0.4 v output short-circuit current *1 i os v o = 0 v or v dd ?? 60 ma input leakage current *2 normal input i li v i = 0 v to v dd - 5 ? 5 m a 3state input i lz input resistance pull-up rpu v il = 0 v 25 50 200 k w pull-down rpd v ih = v dd parameter symbol conditions values unit min. typ. max. h level output voltage v ohsc i oh = - 7 ma 2 ? v dd v l level output voltage v olsc i ol = 48 ma v ss ? 0.5 v input hysteresis voltage width v hys ? 0.2 ?? v
mb86616 22 (3) ieee 1394 driver and comparator ? driver (v dd3 = 3.3 0.3 v, vss = 0 v, ta = 0 to 70 c) ? comparator (v dd3 = 3.3 0.3 v, vss = 0 v, ta = 0 to 70 c) (4) supply current (v dd3 = 3.3 0.3 v, v dd5 = 5.0 0.5 v, vss = 0 v, ta = 0 to 70 c) parameter symbol conditions values unit min. typ. max. differential output voltage v od r l = 56 w 172 ? 265 mv common-mode output current s100 i cm driver enable, signaling off - 0.81 ? 0.44 ma s200 i sp 200 s200 speed signaling enable - 2.53 ?- 4.84 ma s400 i sp 400 s400 speed signaling enable - 8.10 ?- 12.40 ma off-state voltage v off driver disable ?? 20 mv common-mode output voltage s100 v om driver enable, signaling off 1.665 ? 2.015 v s200 v sp 200 s200 speed signaling enable 1.438 ? 2.015 v s400 v sp 400 s400 speed signaling enable 1.030 ? 2.015 v parameter symbol conditions values unit min. typ. max. common-mode input current i ic driver disable - 20 ? 20 m a arbitration comparator h-level detection v ach ? 168 ?? mv z-level detection v acz ?- 89 ? 89 mv l-level detection v acl ??? 168 mv port-status comparator connection detection v pch ? 1.0 ?? v disconnection detection v pcl ??? 0.6 v parameter symbol conditions values unit min. typ. max. supply current (3.3 v power supply) i dd3 ??? 300 ma supply current (5.0 v power supply) i dd5 ??? 100 ma
mb86616 23 2. ac characteristics (1) clock input note1 : the maximum value assumes the minimum speed (1/16) set by the clock gear feature. note2 : the values are transfer rates at s100/s200/s400. parameter symbol pin name values unit min. typ. max. clock frequency f c sclk ? 24.576 ? mhz clock cycle time t c ? 1/f c ? ns h and l level clock pulse widths t wch , t wcl 15 ?? ns clock rise time, clock fall time t cr , t cf ?? 3ns clock input to each block cpu block f cpu ?? 24.576 ? mhz t cpu ?? 1/fcpu ? ns ieee 1394 block f 1394 ?? 393.216 ? mhz scsi block f scsi ?? 39.322 ? mhz t scsi ?? 1/fscsi ? ns exchange block f exc ?? 39.322 ? mhz cpu block machine clock (note 1) t cyc ? tcpu ? 16 tcpu ns ieee 1394 bus (note 2) f 1394b ? 98.304 196.608 393.216 mhz scsi bus (synchronous transfer) f scsib ? 1.229 ? 19.661 mhz 0.25 v dd sclk 0.65 v dd t wch t c t wcl t cf t cr
mb86616 24 (2) reset input parameter symbol pin name values unit min. typ. max. l level reset pulse width t wrsl reset 5 tcp ?? ns t wrsl reset
mb86616 25 ) (3) external bus interface (flash rom interface) 3-1 bus read (load pin capacitance = 30 pf) * : n is the number of wait cycle.(no wait ; n = 0) the number of wait cycle is set by external pin control registor. parameter symbol pin name values unit min. max. address cycle time t acyc a01 to a18, cs (2 + n*) tcyc - 10 ? ns valid address ? rd t avrl a01 to a18, cs , rd tcyc / 2 - 13 ? ns rd l level pulse width t rlrh rd (1 + n*) tcyc - 25 ? ns rd ? valid data t rldv rd , d00 to d15 ? (1 + n*)tcyc - 30 ns rd -? data hold t rhdx rd , d00 to d15 0 ? ns valid address ? valid data t avdv a01 to a18, cs , d00 to d15 ? (3 / 2 + n*)tcyc - 10 ns rd -? valid address t rhax rd , a01 to a18, cs tcyc / 2 - 20 ? ns a01 to a18 d00 to d15 cs rd t acyc t avrl t rhax t rhdx t rldv t avdv t rlrh
mb86616 26 3-2 bus write (load pin capacitance = 30 pf) * : n is the number of wait cycle.(no wait ; n = 0) the number of wait cycle is set by external pin control registor. (4) ieee 1394 driver * : measurement conditions : c l = 10 pf, r l = 56 w parameter symbol pin name values unit min. max. address cycle time t acyc a01 to a18, cs (2 + n*) tcyc - 10 ? ns valid address ? wr t avwl a01 to a18, cs , wr tcyc / 2 - 13 ? ns wr l level pulse width t wlwh wr (1 + n*) tcyc - 20 ? ns written data ? wr - t dvwh wr , d00 to d15 (1 + n*) tcyc - 25 ? ns wr -? data hold t whdx wr , d00 to d15 tcyc / 2 - 15 ? ns wr -? valid address t whax wr , a01 to a18, cs tcyc / 2 - 15 ? ns parameter symbol pin name values unit min. max. transmission jitter t jt tpa, tpa , tpb, tpb ? 0.15 ns transmission skew t dk ? 0.10 ns transmission rise time, fall time * t dr , t df ? 1.2 ns a01 to a18 d00 to d15 cs wr t acyc t avwl t whax t whdx t dvwh t wlwh
mb86616 27 (5) scsi interface 5-1 target selection operation (with arbitration) parameter symbol pin name values unit min. max. sel ? bsy - ts011 sel , bsy 0 ? ns id assert ? bsy - ts012 db0 to db7 , dbp , bsy 0 ? ns io -? bsy - ts013 io , bsy 0 ? ns bsy -? bsy ts014 bsy 18 tscsi 19 tscsi + 20 ns bsy ? sel - ts015 bsy , sel 0 ? ns bsy ? id hold ts016 db0 to db7 , dbp , bsy 10 ? ns sel -? phase signal output ts017 sel , io cd , msg 9 tscsi 10 tscsi + 20 ns sel db0 to db7, dbp io, cd, msg bsy t s 011 t s 012 t s 013 t s 017 t s 015 t s 016 t s 014
mb86616 28 5-2 target selection operation (without arbitration) parameter symbol pin name values unit min. max. id assert ? sel ts021 db0 to db7 , dbp , sel 0 ? ns io -? sel ts022 io , sel 0 ? ns sel ? bsy ts023 sel , bsy 18 tscsi 19 tscsi + 20 ns bsy ? sel - ts015 bsy , sel 0 ? ns bsy ? id hold ts016 bsy , dbp db0 to db7 10 ? ns sel - ? phase signal output ts017 sel , io , cd , msg 9 tscsi 10 tscsi + 20 ns sel db0 to db7, dbp io, cd, msg bsy t s 021 t s 022 t s 017 t s 015 t s 016 t s 023
mb86616 29 5-3 initiator selection operation (with arbitration) * : scsi block tcl register value parameter symbol pin name values unit min. max. bus free ? bsy ts031 bsy (21 + n*) tscsi (22 + n*) tscsi + 20 ns bsy ? self-id output ts032 bsy , dbp , db0 to db7 015ns bsy ? sel ts033 bsy , sel 128 tscsi - 10 128 tscsi + 15 ns sel ? atn & id output ts034 sel , atn , dbp , db0 to db7 52 tscsi - 10 52 tscsi + 15 ns id output ? bsy - ts035 db0 to db7 , dbp , bsy 8 tscsi - 10 8 tscsi + 15 ns bsy ? sel - & id hold ts036 bsy , sel , dbp , db0 to db7 8 tscsi 9 tscsi + 20 ns sel db0 to db7, dbp atn bsy t s 032 t s 033 t s 035 t s 036 t s 034 t s 031
mb86616 30 5-4 initiator selection operation (without arbitration) * : scsi block tcl register value parameter symbol pin name values unit min. max. bus free ? id output ts041 db0 to db7 , dbp (21 + n*) tscsi (22 + n*) tscsi + 10 ns id output ? sel & atn ts042 db0 to db7 , dbp , sel , atn 44 tscsi - 15 44 tscsi + 10 ns bsy ? sel - & id hold ts036 bsy , sel , dbp , db0 to db7 8 tscsi 9 tscsi + 20 ns sel db0 to db7, dbp atn bsy t s 036 t s 042 t s 041
mb86616 31 5-5 target reselection operation * : scsi block tcl register value parameter symbol pin name values unit min. max. bus free ? bsy ts031 bsy (21 + n*) tscsi (22 + n*) tscsi + 20 ns bsy ? self-id output ts032 bsy , dbp , db0 to db7 015ns bsy ? sel ts033 bsy , sel 128 tscsi - 10 128 tscsi + 15 ns sel ? phase signal & id output ts051 sel , io , cd , msg , dbp , db0 to db7 52 tscsi - 10 52 tscsi + 15 ns id output ? bsy - ts035 db0 to db7 , dbp , bsy 8 tscsi - 10 8 tscsi + 15 ns bsy ? bsy output ts052 bsy 8 tscsi 9 tscsi + 20 ns bsy output ? sel - & id hold ts053 bsy , sel , dbp , db0 to db7 4 tscsi 9 tscsi + 20 ns sel io cd, msg db0 to db7, dbp bsy t s 035 t s 052 t s 053 t s 051 t s 032 t s 031 t s 033
mb86616 32 5-6 initiator reselection operation parameter symbol pin name values unit min. max. sel ? bsy - ts011 sel , bsy 0 ? ns id assert ? bsy - ts012 db0 to db7 , dbp , bsy 0 ? ns io ? bsy - ts061 io , bsy 0 ? ns bsy -? bsy ts014 bsy 18 tscsi 19 tscsi + 20 ns bsy ? sel - ts015 bsy , sel 0 ? ns bsy ? id hold ts016 bsy , dbp , db0 to db7 10 ? ns bsy ? io hold ts062 bsy , io 10 ? ns sel -? bsy (output stop) ts063 sel , bsy 8 tscsi 9 tscsi + 20 ns sel io db0 to db7, dbp bsy t s 015 t s 063 t s 016 t s 012 t s 061 t s 062 t s 011 t s 014
mb86616 33 5-7 target asynchronous transfer (req/ack timing) note1 : the ack rise to req fall time is regulated by (ts072 + ts073 + ts074) or ts075, whichever is longer. note2 : in the following cases, the time regulation is not applied because data transfer is aborted. the data register is empty during data output to the scsi bus. the data register is full during data input from the scsi bus. parameter symbol pin name values unit min. max. req ? ack ts071 req , ack 0 ? ns ack ? req - ts072 ack , req 025ns req -? ack - ts073 req , ack 0 ? ns ack -? req (note 2) ts074 ack , req 025ns ack ? req (notes 1, 2) ts075 ack , req 8 tscsi 9 tscsi + 5ns ack req t s 073 t s 074 t s 075 t s 071 t s 072
mb86616 34 5-8 target asynchronous transfer (data output) parameter symbol pin name values unit min. max. io ? data bus drive ts081 io , dbp , db0 to db7 33 tscsi 34 tscsi + 10 ns data output assert ? req ts082 db0 to db7 , dbp , req 8 tscsi - 5 ? ns ack ? data hold ts083 ack , dbp , db0 to db7 0 ? ns ack io db0 to db7, dbp req t s 083 t s 082 t s 081
mb86616 35 5-9 target asynchronous transfer (data input) parameter symbol pin name values unit min. max. io -? data bus driving stop ts091 io , dbp , db0 to db7 010ns data setup ? ack ts092 db0 to db7 , dbp , ack 10 ? ns req -? data hold ts093 req , dbp , db0 to db7 5 ? ns ack io db0 to db7, dbp req t s 093 t s 092 t s 091
mb86616 36 5-10 target synchronous transfer (req/ack timing) * : value set in bits 3 to 0 in the scsi block tmod register parameter symbol pin name values unit min. max. req assert time ts101 req n* tscsi ? ns req negate time ts102 req n* tscsi ? ns ack assert time ts103 ack 10 ? ns ack negate time ts104 ack 10 ? ns ack cycle time (1) ts105 ack 1 tscsi ? ns ack cycle time (2) ts106 ack 3 tscsi ? ns ack req t s 101 t s 102 t s 103 t s 104 t s 105 t s 106
mb86616 37 5-11 target synchronous transfer (req output delay time) note : the minimum time from the reception of ack in the (n-m) -th byte to the output of req in the n-th byte with maximum offset count = m. the following timing chart assumes that req output is aborted because output of req in the n-1-th byte has made the number of offsets the maximum offset count = m. the maximum offset count is set by bits 7 to 4 in the scsi block transfer mode register. parameter symbol pin name values unit min. max. req output delay time (note) ts111 ack , req 3 tscsi 4 tscsi + 10 ns ack req t s 111 n - 2n - 1 n - m n
mb86616 38 5-12 target synchronous transfer (data output) * : value set in bits 3 to 0 in the scsi block tmod register parameter symbol pin name values unit min. max. io ? data bus drive ts081 io , dbp , db0 to db7 33 tscsi 34 tscsi + 10 ns data output assert ? req ts121 db0 to db7 , dbp , req 8 tscsi - 5 ? ns ts122 db0 to db7 , dbp , req n* tscsi - 5 ? ns req ? data hold ts123 db0 to db7 , dbp , req n* tscsi ? ns io db0 to db7, dbp req t s 122 t s 121 asserted data t s 123 t s 081
mb86616 39 5-13 target synchronous transfer (data input) parameter symbol pin name values unit min. max. io -? data bus driving stop ts091 io , dbp , db0 to db7 010ns data setup ? ack ts131 db0 to db7 , dbp , ack 5 ? ns ack ? data hold ts132 ack , dbp , db0 to db7 5 ? ns io db0 to db7, dbp ack t s 131 t s 132 t s 091
mb86616 40 5-14 initiator asynchronous transfer (req/ack timing) note1 : applies to data output to the scsi bus. the req rise to ack fall time is regulated by (ts143 + ts144 + ts141) or ts145, whichever is longer. note2 : applies to data input from the scsi bus. the req rise to ack fall time is regulated by (ts143 + ts144 + ts141) or ts146, whichever is longer. the req fall to ack rise time is regulated by (ts141 + ts142 + ts143) or ts147, whichever is longer. note3 : in the following cases, either time regulation is not applied because data transfer is aborted. the data register is empty during data output to the scsi bus. the data register is full during data input from the scsi bus. at n is output upon detection of a parity error during data input from the scsi bus. during transfer of the first or last byte parameter symbol pin name values unit min. max. req ? ack (note 3) ts141 req , ack 025ns ack ? req - ts142 ack , req 0 ? ns req -? ack - (note 3) ts143 req , ack 01 tscsins ack -? req ts144 ack , req 0 ? ns req -? ack (notes 1, 3) ts145 req , ack 8 tscsi 9 tscsi + 5ns req -? ack (notes 2, 3) ts146 req , ack 4 tscsi 5 tscsi + 5ns req ? ack - (notes 2, 3) ts147 req , ack 8 tscsi 9 tscsi + 5ns req ack t s 145, t s 146 t s 142 t s 143 t s 144 t s 141 t s 147
mb86616 41 5-15 initiator asynchronous transfer (data output) parameter symbol pin name values unit min. max. io -? data bus drive ts151 io , dbp , db0 to db7 010ns phase signal assert ? req ts152 io , cd , msg , req 30 ? ns data output assert ? ack ts153 db0 to db7 , dbp , ack 8 tscsi - 5 ? ns req -? data hold ts154 req , dbp , db0 to db7 0 ? ns ack -? phase signal hold ts155 ack , io , cd , msg 10 ? ns io db0 to db7, dbp req ack t s 152 t s 151 t s 155 t s 153 asserted data t s 154 cd, msg
mb86616 42 5-16 initiator asynchronous transfer (data input) parameter symbol pin name values unit min. max. io ? data bus drive stop ts161 io , dbp , db0 to db7 ? 30 ns phase signal assert ? req ts152 io , cd , msg , req 30 ? ns data setup ? req ts162 db0 to db7 , dbp , req 10 ? ns ack ? data hold ts163 ack , dbp , db0 to db7 5 ? ns ack -? phase signal hold ts155 ack , io , cd , msg 10 ? ns io db0 to db7, dbp req ack t s 152 t s 161 t s 155 t s 162 t s 163 cd, msg
mb86616 43 5-17 initiator synchronous transfer (req/ack timing) * : value set in bits 3 to 0 in the scsi block tmod register parameter symbol pin name values unit min. max. req assert time ts171 req 10 ? ns req negate time ts172 req 10 ? ns req cycle time (1) ts173 req 1 tscsi ? ns req cycle time (2) ts174 req 3 tscsi ? ns ack assert time ts175 ack n* tscsi ? ns ack negate time ts176 ack n* tscsi ? ns ack req t s 175 t s 176 t s 171 t s 172 t s 173 t s 174
mb86616 44 5-18 initiator synchronous transfer (ack output delay time) note1 : the minimum time from the reception of req in the n-th byte to the output of ack in the n-th byte. note2 : applies to data input from the scsi bus, with the maximum offset count set to 8 to 15. the maximum offset count is set by bits 7 to 4 in the scsi block transfer mode register. note3 : applies in any case other than note 2. parameter symbol pin name values unit min. max. ack output delay time (1) (notes 1, 2) ts181 req , ack 9 tscsi 12 tscsi + 5ns ack output delay time (2) (notes 1, 3) ts182 req , ack 3 tscsi 4 tscsi + 5ns ack req t s 181, t s 182 n - 1 n n + 1 n n - 1 n - 2
mb86616 45 5-19 initiator synchronous transfer (data output) * : value set in bits 3 to 0 in the scsi block tmod register note : the "data output assert to ack fall" time is regulated by ts191 or ts192, whichever is shorter. parameter symbol pin name values unit min. max. io -? data bus drive ts151 io , dbp , db0 to db7 010ns phase signal assert ? req ts152 io , cd , msg , req 30 ? ns data output assert ? ack (note ) ts191 db0 to db7 , dbp , ack 8 tscsi - 5 ? ns ts192 db0 to db7 , dbp , ack n* tscsi - 5 ? ns ack ? data hold ts193 db0 to db7 , dbp , ack n* tscsi ? ns ack -? phase signal hold ts155 ack , io , cd , msg 10 ? ns io db0 to db7, dbp req ack t s 152 t s 151 t s 155 t s 191 asserted data t s 193 t s 192 cd, msg
mb86616 46 5-20 initiator synchronous transfer (data input) parameter symbol pin name values unit min. max. io ? data bus drive stop ts161 io , dbp , db0 to db7 ? 30 ns phase signal assert ? req ts152 io , cd , msg , req 30 ? ns data setup ? req ts162 db0 to db7 , dbp , req 5 ? ns req ? data hold ts201 req , dbp , db0 to db7 5 ? ns ack -? phase signal hold ts155 ack , io , cd , msg 10 ? ns io db0 to db7, dbp req ack t s 152 t s 161 t s 155 t s 162 t s 201 cd, msg
mb86616 47 5-21 arbitration failure parameter symbol pin name values unit min. max. arbitration start ? bsy - & self-id output stop ts211 bsy , dbp , db0 to db7 128 tscsi - 10 128 tscsi + 15 ns other devices sel ? bsy - & self-id output stop ts212 sel , bsy , db0 to db7 , dbp 8 tscsi 9 tscsi + 20 ns t s 212 t s 211 bsy sel db0 to db7, dbp
mb86616 48 5-22 selection/reselection time-out parameter symbol pin name values unit min. max. time out interrupt reset ? scsi bus clear ts222 sel , io , dbp , db0 to db7 3 tscsi - 10 3 tscsi + 15 ns t s 221 write strobe sel io db0 to db7, dbp
mb86616 49 5-23 target disconnect operation parameter symbol pin name values unit min. max. rel command issue ? bsy - ts231 bsy 3 tscsi - 10 3 tscsi + 15 ns rel command issue ? scsi bus clear ts232 req , io , cd , msg , dbp , db0 to db7 3 tscsi - 10 3 tscsi + 15 ns t s 231 t s 232 write strobe bsy req, io, cd, msg db0 to db7, dbp
mb86616 50 5-24 initiator disconnect operation parameter symbol pin name values unit min. max. bsy -? scsi bus clear ts241 bsy , ack , atn , dbp , db0 to db7 ? 21 tscsi + 20 ns t s 241 bsy atn, ack db0 to db7, dbp
mb86616 51 5-25 reset condition detection parameter symbol pin name values unit min. max. reset condition detection time ts251 rst 12 tscsi ? ns rst ? scsi bus clear ts252 all scsi bus pins ? 12 tscsi + 20 ns rst scsi bus signals other than rst t s 251 t s 252
mb86616 52 5-26 reset condition generation parameter symbol pin name values unit min. max. write 1 to rst out bit ? rst ts261 rst ? 10 ns rst ? scsi bus clear ts262 all scsi bus pins ? 10 ns write 0 to rst out bit ? rst - ts263 rst ? 10 ns write strobe rst t s 261 t s 262 scsi bus signals other than rst
mb86616 53 (6) ieee 1394/scsi/exchange block register access 6-1 read operation parameter symbol pin name values unit min. max. address setup t ravrl a01 to a09, cs , rd 10 ? ns address hold t rrhax a01 to a09 cs , rd 5 ? ns rd l level pulse width t rrlrh rd 40 ? ns rd ? valid data t rrldv rd , d00 to d15 ? 25 ns rd -? data hold t rrhdx rd , d00 to d15 5 ? ns wr -? rd t rwhrl wr , rd 45 ? ns t ravrl t rwhrl t rrldv t rrhax t rrhdx t rrlrh a01 to a09 cs rd d00 to d15 wr
mb86616 54 6-2 write operation parameter symbol pin name values unit min. max. address setup t ravwl a01 to a09, cs , wr 10 ? ns address hold t rwhax a01 to a09 cs , wr 5 ? ns wr l level pulse width t rwlwh wr 40 ? ns data setup t rdvwh wr , d00 to d15 30 ? ns data hold t rwhdx wr , d00 to d15 5 ? ns t ravwl t rdvwh t rwhax t rwhdx t rwlwh a01 to a09 cs wr d00 to d15
mb86616 55 6-3 register access recovery time ? continuous read/write operation shown below is the timing of continuously reading or writing the register at the same address. note : applies to access to an internal register of the ieee 1394 block in forced sleep mode. ? write operation ? read operation shown below is the timing of reading after writing the register at the same address. note : applies to access to an internal register of the ieee 1394 block in forced sleep mode. parameter symbol pin name values unit min. max. rd (wr ) -? rd (wr ) t rwhrwl1 rd /wr 25 ? ns rd (wr ) -? rd (wr ) (note) t rwhrwl2 wr /rd 45 ? ns parameter symbol pin name values unit min. max. wr -? rd t wrhrdl1 wr , rd 80 ? ns wr -? rd (note ) t wrhrdl2 wr , rd 160 ? ns t rwhrwl1, 2 rd (wr) wr t wrhrdl1, 2 rd
mb86616 56 ? ieee 1394 block phy/link register read operation shown below is the timing from writing the phy/link register address set register (address 002038h) to reading the phy/link access port (address 00203ah) to access the phy-link register in the ieee 1394 block. note : applies to access in forced sleep mode. ? ieee 1394 block phy/link register write operation shown below is the timing from writing the phy/link register address set register (address 002038h) to writing the phy/link access port (address 00203ah) to access the phy-link register in the ieee 1394 block. parameter symbol pin name values unit min. max. wr -? rd t plwhrl1 wr , rd 100 ? ns wr -? rd (note ) t plwhrl2 wr , rd 200 ? ns parameter symbol pin name values unit min. max. wr -? wr t plwhwl1 wr 100 ? ns wr write to address 002038h read from address 00203ah t plwhrl1, 2 rd t plwhwl1, 2 wr write to address 002038h write to address 00203ah
mb86616 57 n n n n system configuration examples 1. recommended connection example of ieee 1394 port (1 port) tpbias tpa tpa tpb tpb r0 cps tpb tpb tpa tpa 56 w 1% 56 w 1% 56 w 1% 56 w 1% 5.1 k w 1% 5.1 k w 1% 510 k w 5% 91 k w 5% 1 m f 5% 250 pf 5% cable cable cable cable cable power (8 to 33 v) cable power cable ground
mb86616 58 2. recommended connection example of internal pll loop filter 5.1 k w 1% 390 w 5% 3300 pf 5% rf fil
mb86616 59 3. sample system configurations ? normal mode (using the internal cpu) tpa0 tpa0 tpb0 tpb0 tpbias0 ieee1394 connector0 tpa1 tpa1 tpb1 tpb1 tpbias1 pmode pwr1 to pwr3 a01 to a18 md0 to md2 modeb, modec modea sclk reset wr rd cs d00 to d15 p74 to p76, p90 to p93 ieee1394 connector1 mb86616 external flash rom scsi connector rst bsy sel msg cd io req ack atn db0 to db7 dbp
mb86616 60 ? external cpu mode tpa0 tpa0 tpb0 tpb0 tpbias0 ieee1394 connector0 tpa1 tpa1 tpb1 tpb1 tpbias1 pmode pwr1 to pwr3 a01 to a09 md0 to md2 modeb, modec modea sclk reset wr rd cs d00 to d15 int0 int1 ieee1394 connector1 mb86616 external cpu scsi connector rst bsy sel msg cd io req ack atn db0 to db7 dbp
mb86616 61 n n n n ordering information part number package remarks MB86616PFV-G-BND 144-pin plastic lqfp (fpt-144p-m08)
mb86616 62 n n n n package dimension 144-pin plastic lqfp (fpt-144p-m08) dimensions in mm (inches) c 2000 fujitsu limited f144019s-1c-3 details of "a" part details of "b" part 0.50?.20(.020?008) 0 10 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 22.00?.30(.866?012)sq 20.00?.10(.787?004)sq 0.20?.10 (.008?004) 0.08(.003) m 0.15?.05 (.006?002) 1.70(.67)max 0(0)min (stand off) 21.00 17.50 (.827) nom (.686) ref "a" "b" 36 37 72 73 108 109 144 1 index 0.50(.0197)typ lead no. (mounting height) 0.10(.004)
mb86616 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0008 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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